Andes Technology unveils AndesCore AX60 series - New Electronics

2 years ago 34

Andes Technology, a supplier of precocious efficiency, debased powerfulness 32/64-bit RISC-V processor cores person unveiled the AndesCore AX60 bid of powerfulness and country businesslike out-of-order 64-bit processors.

The household of processors is intended to tally heavy-duty OS and applications with compute intensive requirements specified arsenic precocious driver-assistance systems (ADAS), artificial quality (AI), augmented/virtual world (AR/VR), datacentre accelerators, 5G infrastructure, high-speed networking, and endeavor storage.

The archetypal subordinate of the AX60 series, the AX65, supports the latest RISC-V architecture extensions specified arsenic the scalar cryptography hold and spot manipulation extension. It is simply a 4-way superscalar with Out-of-Order (OoO) execution successful a 13-stage pipeline. It fetches 4 to 8 instructions per rhythm guided by highly close TAGE subdivision predictor with loop prediction to guarantee fetch efficiency. It past decodes, renames and dispatches up to 4 instructions into 8 execution units, including 4 integer units, 2 afloat load/store units, and 2 floating-point units. Besides the load/store units, the AX65’s assertive representation subsystem besides includes divided 2-level TLBs with aggregate concurrent array walkers and up to 64 outstanding load/store instructions.

The AX65 supports multicore clump with cache coherence to standard retired performance. Each halfway has 64KB backstage acquisition and information caches. The clump contains up to 8 cores, an in-cluster coherence manager and a shared cache up to 8MB. Its IO coherence interface keeps each AX65 caches coherent with respect to the outer IO transactions and allows easiness of SoC integration. The coherence manager and the shared cache tin usage a timepiece asynchronous to the cores for wide show optimisation successful SoC implementations. In addition, AX65 supports RISC-V modular outer debug and acquisition hint interfaces to facilitate accelerated strategy development, investigation and debugging.

“Our ngo is to supply a broad line-up of processor IPs to enactment a wide scope of applications from tiny MCUs to datacentre accelerators, connection businesslike power processing arsenic good arsenic almighty compute acceleration, and tally bare metal, RTOSes and Linux. We are excited to denote our top-of-the-line household of processors, the AX60 series, to further grow our portfolio,” said Dr. Charlie Su, President and CTO of Andes Technology.

“The AX65 is to connection 2x show successful ample benchmarks implicit the erstwhile high-end core, the AX45, astatine the aforesaid frequency. In addition, it tin run astatine 2.5GHz astatine 7nm process, 25% implicit the AX45. With the large boost successful performance, the AX65 processor addresses the emerging requirements of a wide scope of applications looking to rise power processor show successful the existent high-performance SoCs.”

The AndesCore AX65 volition beryllium disposable for pb customers successful mid-2023 done the aboriginal entree programme and for wide customers by the extremity of the aforesaid year.

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